//Author   : Alex Zhang (alzhang@sensylink.com)
//Date     : 09-04-2017
//Comment  : 2-order Cascade Integrator Comb. 
//                       (1-Z^-(RM))2
//             H(z) = ----------------
//                       (1-Z^-1)^2


module sinc2(
input            bit_stream,
input            clk       , 
input            resetn    ,
output[14:0]     temp      
);

wire  clk_div_256;
reg [7:0] clk_count;
always @(posedge clk or negedge resetn)
  if (~resetn)
    clk_count <= 'h0;
  else 
    clk_count <= clk_count + 1;

assign #1us clk_div_256 = &clk_count; 

reg [13:0]  Count1;
always @(posedge clk or negedge resetn)
  if (~resetn) begin 
     Count1 <= 'h0;
  end else begin 
     if (clk_div_256 )
       Count1 <= bit_stream ? 'h1 :0 ;
     else 
       Count1 <= bit_stream ? Count1 + 1: Count1;
  end 

  

reg [15:0]  ZQ_0;
always @(posedge clk or negedge resetn)
  if (~resetn) begin 
      ZQ_0 <= 'h0;
  end else begin 
      //ZQ_0 <= bit_stream ? ZQ_0 + 1'b1 : ZQ_0 -1'b1;
      ZQ_0 <= bit_stream ? ZQ_0 + 1'b1 : ZQ_0 ;
  end 

reg [15:0] ZQ_1;
always @(posedge clk or negedge resetn)
  if (~resetn) begin 
      ZQ_1 <= 0;
  end else begin 
      ZQ_1 <= ZQ_0 + ZQ_1;
  end  

//Frequency down step
reg [15:0] ZQ_2;
always @(posedge clk_div_256 or negedge resetn)
  if (~resetn)
    ZQ_2 <= 'h0;
  else 
    ZQ_2 <= ZQ_1 ;

reg [15:0] ZQ_3;
reg [15:0] ZQ_4;

wire [15:0] Comb1 ; 
wire [15:0] Comb2 ;
assign  Comb1 = ZQ_2 - ZQ_1;
assign  Comb2 = ZQ_3 + Comb1;
always @(posedge clk_div_256 or negedge resetn)
  if (~resetn) begin 
     ZQ_3 <= 'h0;
     ZQ_4 <= 'h0;
  end else begin 
     ZQ_3 <= -Comb1;
     ZQ_4 <= -Comb2;
  end 

assign temp = ZQ_4;



endmodule 
